1. Field of the Invention
This invention relates in general to a communication system, and more particularly to a pseudo-noise encoded digital data clock recovery circuit at a receiver of a communication system.
2. Description of Related Art
In communication systems, signals or data are modulated at a transmission end before they are transmitted to a transmission media. At a receiving end, the signals are recovered/demodulated/acquired. Due to the noise and other defects in the transmission media, the received signals often carry errors, such as noise signals, phase shifts, etc. To overcome these problems, communication systems often use an error correcting technique in a recovery circuit at the receiving end to reliably recover the original signals or data. One technique is to use a pseudo-noise encoded digital data clock recovery circuit by correlating a pseudo-noise sequence which is used to encode/modulate the original signals or data at the transmission end with the received signals. More specifically, a serial stream of digital signals or data is modulated by a pseudo-noise sequence known to both a transmitter and a receiver of a communication system. The pseudo-noise sequence is a finite length pseudo-random sequence of bits (e.g., 101100111101000). In this type of modulation, “1” bits in the original data stream are replaced by the true pseudo-noise sequence (e.g., 101100111101000) and “0” bits are replaced by the complement of the true pseudo-noise sequence (e.g. 010011000010111), respectively. Thus, the bit rate of the modulated data stream is M times the bit rate of the original data stream where M is the number of bits in the pseudo-noise sequence, e.g. M is fifteen (15).
Traditionally, the individual bits in a pseudo-noise sequence are often referred to as “chips”. Henceforth, the bits in the original data stream is hereinafter referred to as “bits”, and the pseudo-noise bits in the modulated data stream is hereinafter referred to as “chips”.
In the existing communication systems, an additional modulation step is usually used, whereby an analog carrier signal is modulated by the pseudo-noise modulated data stream for effective transmission over a physical medium (e.g., PSK, FM). In some systems, a received signal is first demodulated to recover the pseudo-noise modulated chip stream generated by at the transmitter, while other systems recover an original bit stream directly from the received analog signal in one demodulation step.
Typically, the receiver can recover the original bit stream by looking for matches of the pseudo-noise sequence or its complement, within the incoming chip stream. However, if the transmission media is noisy resulting in frequent chip errors, a more sophisticated method is needed to recover the data. The greater the chip error rate, the more difficult it is to recognize the pseudo-noise sequence or its complement in a received chip stream. A bit period is defined as the time interval spanned by one bit before pseudo-noise modulation and by the M chips of the true or complement pseudo-noise sequence after modulation. If an alignment of the original bit period within the chip stream is known, then the data can be recovered by comparing the chips in the pseudo-noise sequence with their counterparts in the incoming chip stream and counting up the matches. If the number of matches is close to the number of chips in the pseudo-noise sequence, then the original bit is most likely a One (1 bit). Otherwise, if the number of matches is close to zero, then the original bit is most likely a Zero (0 bit). If the number of matches falls somewhere near the middle of the range, i.e. falls somewhere near the middle between zero and the number of chips in the pseudo-noise sequence, then most likely the presumed alignment of the original bit period is not correct. In fact, the alignment of the bit period within the received chip stream must be precisely identified before the original data can be reliably recovered.
In the existing communication systems, a correct bit period is typically identified by correlating the chip stream with the pseudo-noise sequence. Specifically, a chip stream is shifted through a correlator circuit that, at each shift increment, attempts to match the sequence of chips in the correlator with the pseudo-noise sequence and outputs the number of matching chips. Once a pseudo-noise sequence alignment is found, then the correlator can be used to recover the original data stream. Typically, if the pseudo-noise sequence is chosen carefully, even with a high chip error rate, the correlator will produce a value near one of the extremes of its range, i.e. zero to M, if a bit period of the chip stream is perfectly aligned with the correlator's reference pseudo-noise sequence and a value near the middle of its range otherwise.
In the existing communication systems, an upper and a lower threshold is applied to a correlator output. As a result, a thresholded correlator output is generated. The thresholded correlator output indicates whether the correlator has exceeded either the upper or lower threshold. In other words, the thresholded correlator output indicates whether the correlator output is near one of the extremes and not in the middle. One would expect to see a spike (binary one) on a correlator output every time a true or its complement pseudo-noise sequence in the incoming chip stream comes into alignment with the correlator's reference pseudo-noise sequence. A binary signal, called a “bit clock” or “detection signal”, is derived from the thresholded correlator output. The bit clock or detection signal is a periodic signal which indicates when the output of the correlator should be looked at to determine the original bit stream, i.e., when the bit period of the incoming chip stream is presumed to be aligned with the reference pseudo-noise sequence in the correlator.
The simplest derivation of the bit clock is to use a thresholded correlator output. If the chip error rate is low enough, then this scheme is sufficient to produce a reliable, periodic bit clock with no misaligned or dropped cycles. Ideally, the correlator output does not produce spurious spikes in between bit period boundaries or drops spikes at bit period boundaries. Alternatively, a clock divider, which is resynchronized to spikes of the correlator output when those spikes are deemed to mark true bit boundaries, could generate a bit clock. For example, a bit clock could be generated with a fairly high degree of confidence if the bit clock is resynchronized only after observing some number N consecutive spikes of the same periodicity as the bit rate on the correlator output.
Typically, clocks used at the transmitter and receiver of a communication system are not synchronized because their oscillators are independent. Therefore, the derived bit clock at the receiver often drifts out of phase with respect to a bit period in the transmitted signal unless its synchronization is maintained. The problem of identifying the correct bit period alignment covers not only an initial identification of this alignment (“acquisition”) but also the maintaining of the correct alignment over time (“tracking”). In the existing systems, a correlator output is used to periodically adjust the phase of the bit clock in the same way that the correlator output is used to initially synchronize the bit clock.
Also, in some existing systems, the received chip stream is oversampled by a rate that is the chip rate multiplied by a whole number. The resulting stream is correlated with the pseudo-noise sequence in much the same way as before, except instead of comparing every element in the correlator shift register with the pseudo-noise sequence, every Kth element is compared with the pseudo-noise sequence, where K is the number of samples per chip.
Oversampling techniques have advantages for bit clock phase alignment. In a system using an oversampling technique, a thresholded correlator output would produce a series of K consecutive spikes once every bit period. In theory, the data clock recovery circuit could use the correlator output at any of the sample positions associated with this series. However, with errors in the received chip stream or with phase drift between the transmitter and receiver clocks, the optimal sample position for data recovery is typically the one that occurs in the center of the intervals where this series of spikes is expected on the correlator output.
In receivers where there is one sample per chip, and there is phase drift between the transmitter and the receiver, bit clock tracking is problematic. When the optimal sample position of the correlator output drifts from one position to an adjacent position, the phase of the generated bit clock follows the drift with a small time lag since it takes at least one bit period for the bit clock to synchronize. With multiple samples per chip, the problem is solved. The bit clock phase can be off by one sample position from the optimal sample position but does not compromise the recovery of the data. In receivers where there is only one sample per chip, if the bit clock is off by one sample position, then the recovered data would be erroneous.
In systems where there are multiple samples per chip, chips are generally recovered in a lower error rate when the chips are sampled nearer to the center of the chip period. This results in a more reliable correlator output. Therefore, if the received chip stream is sampled multiple times in each chip period, then the bit clock generator can choose the best sample position within the interval of expected spikes at the thresholded correlator output.
However, in applications with particularly high chip error rates, e.g. 1 in 10 or 1 in 5, the oversampling technique and other techniques described above are not sufficiently robust to align the bit clock with a high degree of confidence. With such error rates, the correlator frequently generates false spikes on its threshold output when a pseudo-noise sequence is not aligned with the bit period of the incoming chip stream and, conversely, the correlator does not generate correct spikes even when a pseudo-noise sequence is aligned with the bit period of the incoming chip stream.
It can be seen then that there is a need for a pseudo-noise encoded digital data clock recovery circuit that reliably synchronizes a bit clock, identifies a correct bit alignment, and tracks the correct bit alignment over time.
It can also be seen that there is a need for a pseudo-noise encoded digital data clock recovery circuit that recovers an original bit stream from a digital chip stream in a noisy transmission media with high error rates.
It is with respect to these and other considerations that the present invention has been made.